Study of Power Loss of Small Time-Step VSC Model in RTDS

In this paper, the power loss of power electronic switches modeled as RTDS small time-step voltage source converter (VSC) is studied. The reduction of time step size and resistance at OFF state can decrease the artificial switching loss in the RTDS small time-step VSC models. Higher noise levels in the RTDS simulations indicate more power loss in the RTDS simulations than in equivalent PSIM simulations. The sensitivity of the power loss and the total harmonic distortion (THD) to parameters, including switch model parameters and interface transformer model parameters are studied. With appropriately selected component model parameters, the power loss of the modeled switches can be reduced.