Title :
EDAC. Proceedings of the European Conference on Design Automation
Abstract :
The following topics were dealt with: formal verification; logic synthesis; fault modelling; layout analysis; data path synthesis; circuit simulation; partitioning; finite state machines; test pattern generation; routing; timing verification; testable circuits; scheduling; switch-level simulation; floorplans; OO approaches; analogue design; combinational circuits; partitioning; and digital simulation
Keywords :
automatic testing; circuit layout CAD; digital simulation; fault location; logic CAD; logic testing; OO approaches; analogue design; circuit simulation; combinational circuits; data path synthesis; digital simulation; fault modelling; finite state machines; floorplans; formal verification; layout analysis; logic synthesis; partitioning; routing; scheduling; switch-level simulation; test pattern generation; testable circuits; timing verification;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam, Netherlands
DOI :
10.1109/EDAC.1991.206333
