• DocumentCode
    3105427
  • Title

    PLATO-a CAD tool for logic synthesis based on decomposition

  • Author

    Luba, Tadeusz ; Kalinowski, Jerzy ; Jasinski, Krzyasztof

  • Author_Institution
    Inst. of Telecommun., Warsaw Univ. of Technol., Poland
  • fYear
    1991
  • fDate
    25-28 Feb 1991
  • Firstpage
    65
  • Lastpage
    69
  • Abstract
    A CAD system for logic synthesis (PLATO system) that exploits logic decomposition to optimize the actual circuit is presented. Unlike the traditional approach, where the partitioning or decomposition follows logic minimization, decomposition process is carried out in the PLATO system as the very first step in the logic synthesis. Experimental results indicate that a significant reduction of the silicon area can be obtained using this new design strategy
  • Keywords
    integrated logic circuits; logic CAD; monolithic integrated circuits; CAD tool; PLATO; decomposition; design strategy; logic synthesis; silicon area; Boolean functions; Circuit synthesis; DH-HEMTs; Input variables; Instruction sets; Logic circuits; Logic design; Logic functions; Minimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation. EDAC., Proceedings of the European Conference on
  • Conference_Location
    Amsterdam
  • Type

    conf

  • DOI
    10.1109/EDAC.1991.206361
  • Filename
    206361