Title :
Formal sizing rules of CMOS circuits
Author :
Auvergne, D. ; Azemard, N. ; Bonzom, V. ; Deschacht, D. ; Robert, M.
Author_Institution :
Lab. d´´Autom. et de Microelectron., Montpellier Univ., France
Abstract :
Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation
Keywords :
CMOS integrated circuits; NAND circuits; adders; circuit layout CAD; logic CAD; logic arrays; CMOS circuits; NAND gates; adder cells; automatically generated layout; delay/area optimal; electrical netlist; irregular inverter arrays; local strategy; matrix style layout implementation; sizing; Adders; Analytical models; Circuit simulation; Circuit synthesis; Delay effects; Equations; Inverters; Parasitic capacitance; Performance analysis; Silicon;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206368
