Concurrent Error Detection in Systolic Array AB^2 Multiplier Using Linear Codes

This investigation is based on a traditional AB² systolic array multiplier to derive a new CED AB2 multiplier using linear block codes. A novel linear encoding algebra is derived to realize parity-check functionality. It is based on the syndrome value, and is adopted to detect errors in the multiplication. Altera FPGA with stratix families to simulate our proposed CED multiplier. In the field GF (2⁷²), the space overhead of the proposed circuit is around 9.1%. The latency overhead only requires extra two clock cycles. The proposed CED architecture can therefore be utilized effectively in fault-tolerant cryptosystems.