• DocumentCode
    3105863
  • Title

    SHARP-looking geometric partitioning

  • Author

    Bapat, S. ; Cohoon, J.P.

  • Author_Institution
    Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
  • fYear
    1991
  • fDate
    25-28 Feb 1991
  • Firstpage
    172
  • Lastpage
    176
  • Abstract
    A new technique, named SHARP, is presented for the partitioning of VLSI integrated circuits. SHARP is a hill-climbing heuristic that is designed to be incorporated into a partitioning-based placement algorithm. Its important features include a geometric decomposition of the layout surface into a `#´-shaped region; a multi-objective function that more accurately represents wire usage than the standard min-cut criterion, and extensive use of Steiner trees. A series of experiments demonstrates that the SHARP technique produces very high quality partitions
  • Keywords
    VLSI; circuit layout CAD; SHARP technique; Steiner trees; geometric decomposition; geometric partitioning; hill-climbing heuristic; multi-objective function; partitioning of VLSI integrated circuits; partitioning-based placement algorithm; wire usage; Algorithm design and analysis; Circuit simulation; Computer science; Delay systems; Integrated circuit interconnections; Packaging; Partitioning algorithms; Process design; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation. EDAC., Proceedings of the European Conference on
  • Conference_Location
    Amsterdam
  • Type

    conf

  • DOI
    10.1109/EDAC.1991.206384
  • Filename
    206384