A CMOS analog timing recovery circuit for 180 Mb/s PRML detectors

Timing recovery (TR) is an integral component of a sampling detection system that also contains an equalizer and a partial-response maximum-likelihood (PRML) detector. Although decision-directed minimum-mean-square error (MMSE) timing recovery has recently been implemented in digital read channel chips, analog read channel chips have used modified techniques and cannot be applied to arbitrary partial-response (PR) polynomials. Here the authors present an analog phase locked loop (PLL) for TR. Normally, when the PLL is integrated as part of a sampling detection system, it is provided with sampled signals. The chip presented by the authors uses analog circuitry for phase detection and filtering and a single 3.3 V supply. It is fabricated in a 1.2 /spl mu/m CMOS process available through MOSIS. Capacitors are fabricated using poly top plates and diffusion bottom plates. The key features of this PLL are the architecture and the implementation of the phase detector. This phase detector architecture can be adapted to other PR polynomials and can also work with variable polynomials.