Formal method for self-timed design

Author

Kishinevsky, M.A. ; Kondratyev, A.Y. ; Taubin, A.R.

Author_Institution

R&D Coop Trassa, Leningrad, USSR

fYear

1991

fDate

25-28 Feb 1991

Firstpage

197

Lastpage

201

Abstract

A formal method of self-timed circuit design, based on compact event model-change diagrams (CD), is suggested. This model (CD) seems to be very attractive because of convenient tools for describing the semantics of concurrency which allows one to enhance the specification from distributive class of processes to semimodular ones. The necessary and sufficient conditions of CD correctness and polynomial algorithms of their analysis are introduced. The formal synthesis procedure consider as the set of equivalent transformations of initial specification (inserting to it the additional signals) that exclude some incorrectness (contradiction, abnormality and so on). The Boolean equations of implementing self-timed circuit can be easily obtained from the corrected description

Keywords

VLSI; diagrams; logic design; Boolean equations; compact event model-change diagrams; formal synthesis procedure; initial specification; self-timed circuit design; set of equivalent transformations; Boolean functions; Circuit analysis; Circuit synthesis; Design methodology; Equations; Information analysis; Inverters; Logic circuits; Logic design; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation. EDAC., Proceedings of the European Conference on

Conference_Location

Amsterdam

Type

conf

DOI

10.1109/EDAC.1991.206389

Filename

206389