Title :
Array folding using heuristics and simulated annealing
Author :
Kannan, L.N. ; Sarma, D.
Author_Institution :
Cadence Design Syst., Santa Clara, CA, USA
Abstract :
Array folding is a technique to reduce the area of a logic array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper, a method employing a combination of simulated annealing and heuristic algorithms has been used to find a near optimal solution for both simple and multiple folding of logic arrays. The algorithms developed have been implemented in a computer program called GAMIN-SA. When compared to PLEASURE, GAMIN-SA was seen to perform as good or better with regard to quality of solution and, for the bigger arrays, it was better in terms of run-time as well (multiple folding)
Keywords :
logic arrays; logic design; simulated annealing; GAMIN-SA; PLA; area reduction; array folding; heuristic algorithms; large arrays; multiple folding of logic arrays; near optimal solution; programmable logic arrays; quality of solution; run-time; simulated annealing; Artificial intelligence; Circuits; Compaction; Computational modeling; Computer science; Heuristic algorithms; Input variables; Logic arrays; Programmable logic arrays; Simulated annealing;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206390