DocumentCode
3106006
Title
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
Author
Van Sas, Jos ; Catthoor, Francky ; Vandeput, Peter ; Rossaert, Frank ; De Man, Hugo
Author_Institution
IMEC Lab., Leuven, Belgium
fYear
1991
fDate
25-28 Feb 1991
Firstpage
208
Lastpage
213
Abstract
The CAD implementation of a testability strategy for chips as designed with the Cathedral-II/2nd silicon compilation environment is presented. Emphasis is on the software tools accomplishing the test assembly. These tools are fully integrated with synthesis, place and route and module generation programs. The hierarchy present in the design has been exploited to assemble the test patterns in an hierarchical way. The authors´ approach allows to arrive at a fully testable chip, with a very high fault coverage
Keywords
automatic test equipment; circuit layout CAD; integrated circuit testing; logic testing; multiprocessing systems; parallel architectures; CAD implementation; Cathedral-II/2nd architectural synthesis environment; Cathedral-II/2nd silicon compilation environment; fully testable chip; high fault coverage; software tools; testability strategy; Arithmetic; Assembly; Design automation; Registers; Signal processing; Silicon; Software testing; Software tools; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location
Amsterdam
Type
conf
DOI
10.1109/EDAC.1991.206392
Filename
206392
Link To Document