HITEC: a test generation package for sequential circuits

Presents HITEC, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state. Several new techniques are introduced to improve the performance of test generation. A targeted D element technique is presented, which greatly increases the number of possible mandatory assignments and reduces the over-specification of state variables which can sometimes result when using a standard PODEM algorithm. A technique to use the state knowledge of previously generated vectors for state justification, without the memory overhead of a state transition diagram is presented. For faults that were aborted during the standard test generation phase, knowledge that was gained about fault propagation, by the fault simulator, is used. These techniques, when used together, produce the best published results for the ISCAS89, sequential benchmark circuits