Title :
On the selection of a partial scan path with respect to target faults
Author :
Gundlach, Harald ; Koch, Bernd ; Müller-Glaser, Klaus-Dieter
Author_Institution :
Dept. of Comput. Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
Abstract :
Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path, existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible
Keywords :
automatic test equipment; built-in self test; digital integrated circuits; integrated circuit testing; logic testing; DFT-strategy; design for testability; existing testpatterns; partial scan path; partial scan path selection; remaining faults; short runtimes; target faults; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Clocks; Design for testability; Electrical fault detection; Feedback loop; Pins; Pipelines;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206394
