Title :
An integrated layout system for sea-of-gates module generation
Author :
Duchene, P. ; Declercq, M. ; Kang, S.M.
Author_Institution :
Electron. Labs., Federal Inst. of Technol., Lausanne, Switzerland
Abstract :
Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells
Keywords :
application specific integrated circuits; circuit layout CAD; logic arrays; ASIC; SOG; channelless fashion; flexible leaf cell generation; global routine scheme; integer linear programming methods; integrated layout system; macrocells; medium-size logic circuits; sea-of-gates layout system; sea-of-gates module generation; several hundred transistors; step-wise compaction-rerouting refinement; systematic cell terminal abutment; top-down hierarchy; two layers of metal; Application specific integrated circuits; Consumer electronics; Design methodology; Integer linear programming; Integrated circuit technology; Libraries; Logic circuits; Macrocell networks; Modems; Routing;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206398
