Title :
Test scheduling and controller synthesis in the CADDY-system
Author :
Rudolph, Martin ; Neher, Michael ; Rosenstiel, Wolfgang
Author_Institution :
Forschungszentrum Inf., Karlsruhe Univ., Germany
Abstract :
In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR
Keywords :
automatic testing; built-in self test; graph theory; logic CAD; logic testing; scheduling; BIST; CADDY-system; CASTOR; built-in-self-test; controller synthesis; controller synthesis system; data path graph; test control graph; test schedule problem; Automatic control; Automatic generation control; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Control system synthesis; Hardware; Scheduling algorithm; Signal synthesis;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206408
