Title :
On diagnosing path delay faults in an at-speed environment
Author :
Tekumalla, Ramesh C. ; Venkataraman, Srikanth ; Ghosh-Dastidar, Jayabrata
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Recent techniques for path delay fault diagnosis have addressed the problem in combinational circuits and sequential circuits. The root cause of a path delay fault test failure is narrowed down to a set of functionally sensitized paths and this set is further reduced by post processing the set of passing tests. In this paper, we present a method for narrowing down the suspects further to a set of segments on the failing functionally sensitized paths. The proposed method is implemented and applied to a set of industrial circuits and it is found to be very effective in determining the defective segments that explain excessive delays along paths
Keywords :
automatic testing; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; at-speed environment; combinational circuits; defective segments; fault diagnosis; functionally sensitized paths; industrial circuits; path delay faults; post processing; sequential circuits; Circuit faults; Circuit testing; Clocks; Combinational circuits; Delay effects; Fault diagnosis; Frequency; Sequential analysis; Sequential circuits; Timing;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923414
