Title :
Testable sequential circuit design: a partition and resynthesis approach
Author :
Chou, Richard M. ; Saluja, Kewal K.
Author_Institution :
ASIC Technol., LSI Logic Corp., Milpitas, CA, USA
Abstract :
In this work, we present a divide and conquer approach to improve the testability of large sequential circuits while reducing the area overhead required. Specifically, we partition the circuits into more manageable size circuits for efficient synthesis with testability constraints. We resynthesize each circuit partition and restitch the partitions together to achieve our objectives. Experimental results are presented to demonstrate the effectiveness of our approach
Keywords :
design for testability; divide and conquer methods; fault diagnosis; logic partitioning; logic testing; sequential circuits; area overhead; circuit partition; divide and conquer approach; large sequential circuits; partition and resynthesis approach; testability constraints; testable sequential circuit design; Application specific integrated circuits; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Flip-flops; Sequential analysis; Sequential circuits; System-on-a-chip;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923419
