Practical applications of TCM

Author

Dehesh, H. ; Kerr, Randy

Author_Institution

QUALCOMM Inc., San Diego, CA

fYear

1990

fDate

30 Sep-3 Oct 1990

Firstpage

380

Abstract

The first VLSI implementation of a decoder for multiple-signal (pragmatic) trellis-coded modulation (TCM) is described. Integrated on the same device is an encoder and a decoder for a variable rate binary code. The IC discussed is a 64-state rate 2/3 or 3/4 (used in conjunction with 8 and 16 PSK modulation) TCM decoder. The decoder is also accompanied by a K=7 trellis encoder. Integrated on the TCM decoder is a variable-rate Viterbi decoder (rates 1/2, 3/4, 7/8, 1/3). The chip has been manufactured and tested. The performance in rate 2/3 8 PSK and rate 3/4 16 PSK is shown graphically. Included in each figure is the uncoded performance in addition to the simulated and measured data of the chip. The performance of the chip in the rest of the models is shown. The die size is 320 mils on a side. The device contains 17800 transistors and was fabricated in a state-of-the art 1.0 μm process. The device has attained clock speeds above 30 MHz under nominal conditions. The power consumption at 10 Mbit/s is less than 0.75 W

Keywords

CMOS integrated circuits; VLSI; codecs; phase shift keying; 0.75 W; 1.0 μm process; 10 Mbit/s; 16 PSK modulation; 30 MHz; 8 PSK; IC; TCM decoder; VLSI; clock speeds; measured data; multiple signal modulation; power consumption; simulated data; transistors; trellis-coded modulation; uncoded performance; variable rate binary code; variable-rate Viterbi decoder; Art; Binary codes; Clocks; Decoding; Manufacturing; Phase shift keying; Semiconductor device measurement; Testing; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Military Communications Conference, 1990. MILCOM '90, Conference Record, A New Era. 1990 IEEE

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/MILCOM.1990.117446

Filename

117446