Title :
Multiple scan chain design for two-pattern testing
Author :
Polian, Ilia ; Becker, Bernd
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
Non-standard fault models often require the application of true-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered
Keywords :
automatic test pattern generation; boundary scan testing; design for testability; fault diagnosis; integrated circuit testing; sequential circuits; area overhead constraints; chain-based architecture; fully-automated approach; multiple scan chain design; sequential circuit; test time; two-pattern testing; Application software; Circuit faults; Circuit testing; Combinational circuits; Computer architecture; Computer science; Delay; Integrated circuit technology; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923423
