On probabilistic switch-level simulation for asynchronous circuits

The delay information useful in asynchronous circuits is not the same as in synchronous circuits. Rather than using the worst case delay, usually computed by a critical path analysis, the average case delay over a set of input assignments is a more relevant parameter for an asynchronous system. The authors present a novel, probability-propagation based algorithm to comput the average case switch-level delays. They discuss an implementation of this algorithm which is built on top of RNL, an event-driven switch-level simulator. This implementation takes the same order of time that RNL takes to simulate for one input assignment for determining the average case delays