Title :
Semi-formal test generation for a block of industrial DSP
Author :
Dushina, Julia ; Benjamin, Mike ; Geist, Daniel
Author_Institution :
STMicroelectron., Bristol, UK
Abstract :
Describes an industrial application of the Genevieve test generation methodology. The Genevieve approach uses formal techniques to generate test suites for specific design behaviour. The example, which is a part of the ST100 DSP, was chosen in order to highlight real life problems such as big data structures, complex control logic, and complex environments where it is difficult to determine how to drive the complete system to ensure a given behaviour in the unit under test
Keywords :
automatic testing; data structures; digital signal processing chips; formal specification; hardware description languages; integrated circuit testing; logic testing; Genevieve test generation methodology; ST100 DSP; control logic; data structures; design behaviour; formal techniques; industrial DSP block; semi-formal test generation; unit under test; Circuit testing; Control systems; Data structures; Digital signal processing; Explosions; Integrated circuit testing; Life testing; Signal design; System testing; Timing;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923429
