Title :
Translating system specifications to VHDL
Author :
Narayan, Sanjiv ; Vahid, Frank ; Gajski, Daniel D.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations
Keywords :
program interpreters; specification languages; VHDL; semantic preserving; simulation language; system level abstractions; Clocks; Computational modeling; Computer science; Counting circuits; Decoding; Delay; Hardware; Registers; Specification languages; System-level design;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206432
