DocumentCode :
3106822
Title :
A self-test methodology for IP cores in bus-based programmable SoCs
Author :
Huang, Jing-Reng ; Iyer, Madhu K. ; Cheng, Kwang-Ting
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
198
Lastpage :
203
Abstract :
We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and delivers test patterns to the target IP cores in the SoC and analyzes the test responses. This provides tremendous flexibility in the type of patterns that can be applied to the IP cores without incurring significant hardware overhead. We use a bus based SoC simulation model to validate our test methodology. The test methodology involves addition of a test wrapper that can be configured for specific test needs. The methodology supports at-speed testing for delay faults and stuck-at testing of IP cores implementing full-scan
Keywords :
application specific integrated circuits; boundary scan testing; built-in self test; circuit simulation; delays; fault diagnosis; industrial property; integrated circuit modelling; integrated circuit testing; logic testing; IP cores; at-speed testing; bus based SoC simulation model; bus-based programmable SoCs; delay faults; embedded processor cores; full-scan; hardware overhead; self-test methodology; stuck-at testing; test patterns; test responses; test wrapper; Automatic testing; Built-in self-test; Circuit testing; Delay; Embedded software; Pattern analysis; Software testing; System testing; System-on-a-chip; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
Type :
conf
DOI :
10.1109/VTS.2001.923439
Filename :
923439
Link To Document :
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