Title :
PHIDEO: a silicon compiler for high speed algorithms
Author :
Lippens, P.E.R. ; Van Meerbergen, J.L. ; van der Werf, A. ; Verhaegh, W.F.J. ; McSweeney, B.T. ; Huisken, J.O. ; McArdle, O.P.
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm
Keywords :
computerised signal processing; directed graphs; high definition television; parallel algorithms; pipeline processing; HDTV; PHIDEO; design trajectory; global optimisations; hierarchical flow graphs; high level specification; high speed algorithms; layout; loop boundaries; memory optimisation; real time systems; sampling frequencies; scan conversion algorithm; silicon compiler; target architectural model; Clocks; Clustering algorithms; Flow graphs; Frequency; HDTV; Laboratories; Real time systems; Resource management; Sampling methods; Silicon compiler;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206442
