Title :
Switch and logic-level modeling in EDIF 2 0 0: limitations and proposed solutions
Author :
Mukherjee, Shankar R. ; Mannan, Maqsoodul
Author_Institution :
Nat. Semicond., Santa Clara, CA, USA
Abstract :
In order to transfer switch and gate-level descriptions from one simulation environment to another, information like connectivity, delay, and strength needs to be maintained. Since EDIF is rapidly becoming an industry standard, it can be used as an intermediate format for such transfers. This paper illustrates the effectiveness of EDIF 2 0 0 netlist and logic model views for this purpose and identifies its limitations. Several EDIF writers have been implemented using these concepts. In addition, this paper discusses possible extensions to improve the expressiveness of EDIF
Keywords :
digital simulation; electronic data interchange; logic CAD; EDIF 2 0 0; connectivity; delay; expressiveness; gate-level descriptions; intermediate format; logic-level modeling; netlist; simulation environment; switch level descriptions; Delay; Hardware design languages; Load modeling; Switches;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206445