DocumentCode
3106906
Title
An efficient methodology for generating optimal and uniform march tests
Author
Al-Harbi, Sultan M. ; Gupta, Suneet K.
Author_Institution
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear
2001
fDate
2001
Firstpage
231
Lastpage
237
Abstract
A large number of march tests that provide different fault coverages have been published and a few methodologies have been presented for automatically generating march tests. This paper presents a new methodology for generating optimal and uniform march tests. The new methodology uses a compact representation of faults, generates necessary and sufficient conditions for their detection, and generates tests using the conditions along with the properties of march tests. The methodology is demonstrated as being more efficient than those previously presented. It has been used to (a) generate new optimal tests that are uniform, which are desired to simplify BIST architecture, (b) prove the optimally of some well-known tests such as March C-, and (c) generate a complete set of optimal march tests for different combinations of faults. The proposed approach hence provides memory manufacturers with an optimal test to cover the types of faults that are likely to occur in their memories
Keywords
built-in self test; fault diagnosis; integrated circuit manufacture; integrated circuit testing; integrated memory circuits; production testing; BIST architecture; IC testing; fault combinations; fault coverages; memory ICs; memory manufacture; optimal tests; uniform march tests; Automatic testing; Built-in self-test; Decoding; Fault detection; Manufacturing; Read-write memory; Sufficient conditions;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location
Marina Del Rey, CA
Print_ISBN
0-7695-1122-8
Type
conf
DOI
10.1109/VTS.2001.923444
Filename
923444
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