Title :
Test scheduling for minimal energy consumption under power constraints
Author :
Schuele, Tobias ; Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
Power consumption has become a crucial concern in built-in self-test (BIST) due to the increased switching activity in the circuit under test. In this paper we present a method for scheduling tests which aims at minimizing total energy consumption and test application time under peak power constraints. In contrast to previous approaches, our method takes into account switching activity which occurs in overlapping regions of the subcircuits under test. The key part is a hierarchical approach to power estimation which makes it possible to quickly evaluate the power consumption of partial schedules. Experimental results show that the energy savings range between 54% and 97% in comparison with conventional methods. Test application time can be reduced to the same extent
Keywords :
automatic testing; built-in self test; integrated circuit testing; logic partitioning; logic testing; low-power electronics; scheduling; built-in self-test; circuit under test; hierarchical approach; minimal energy consumption; overlapping regions; partial schedules; peak power constraints; power constraints; power consumption; power estimation; switching activity; test application time; test scheduling; total energy consumption; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Energy consumption; Fault tolerance; Power dissipation; Processor scheduling; Registers; Switching circuits;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923455
