Structure based methods for parallel pattern fault simulation in combinational circuits

The authors present several methods which accelerate fault simulation for combinational circuits using parallel pattern evaluation. The methods are based on an extensive structure analysis of the considered circuit. On the one hand the developed methods aim at a reduction of fan-out stems for which the fault simulation has to be performed and on the other hand at a reduction of gate evaluations during the fault simulation. Of course, all methods support the use of parallel pattern evaluation