Efficient implementation of 10Y lookup table in FPGA

When implementing a mathematical function in h/w, we would like to minimize the required resources. This task is critical in FPGA designs. One of the popular techniques for implementing mathematical functions in h/w, is a lookup table (LUT) based design. In order to reduce the required memory size, the common implementations use a pre-defined set of input values for which the function values are stored in a LUT, and apply a linear or 2^nd order interpolation between these values. In this paper we design an efficient FPGA implementation of a 10^y conversion circuit using this approach. We suggest a simple scaling approach based on the mathematical properties of the 10^y function that allows a more efficient implementation compared to a circuit based on the conventional approach without scaling. We then demonstrate the implementation of this approach in a FPGA.