• DocumentCode
    3107183
  • Title

    Iterative compaction: an improved approach to graph and circuit bisection

  • Author

    Haralambides, J. ; Makedon, F.

  • Author_Institution
    Texas Univ., Richardson, TX, USA
  • fYear
    1991
  • fDate
    25-28 Feb 1991
  • Firstpage
    523
  • Lastpage
    527
  • Abstract
    Given a graph G=(V,E), graph bisection is the problem of finding a partition of the vertex set V in two equal-sized subsets V1 and V2 so that the number of edges between them is minimized. This problem has important applications in circuit partitioning, testing, VLSI design and other network-related problems that apply the divide-and-conquer strategy. The authors introduce a new heuristic approach, called iterative compaction (IC), which employees a node degree based matching and iterative graph compaction. This gives a significant improvement over the performance of known bisection algorithms in both time and quality of the results
  • Keywords
    circuit layout; graph theory; iterative methods; network topology; VLSI design; circuit bisection; circuit partitioning; divide/conquer strategy; heuristic approach; iterative compaction; iterative graph compaction; node degree based matching; testing; Circuit testing; Compaction; Computer science; Heart; Iterative algorithms; Iterative methods; Partitioning algorithms; Routing; Simulated annealing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation. EDAC., Proceedings of the European Conference on
  • Conference_Location
    Amsterdam
  • Type

    conf

  • DOI
    10.1109/EDAC.1991.206462
  • Filename
    206462