Title :
Technology mapping for a two-output RAM-based field programmable gate array
Author :
Filo, David ; Yang, Jerry Chih-Yuan ; Mailhot, Frédéric ; Micheli, Giovanni De
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
The authors present a new approach for performing technology mapping onto field programmable gate arrays (FPGAs). They consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. A heuristic algorithm is described for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. The authors have implemented the algorithm in the program Hydra. Experimental results shows an average of 20% to 25% improvement over other existing programs in mapping area and 67-fold speedup in computing time
Keywords :
combinatorial circuits; graph theory; logic CAD; logic arrays; random-access storage; FPGA primitives; Hydra; circuit decomposition; combinational logic functions; field programmable gate array; five-input RAM-based cells; logic functional sharing; shared input graph; technology mapping; two-output RAM-based; Equations; Field programmable gate arrays; Heuristic algorithms; Input variables; Integrated circuit interconnections; Integrated circuit technology; Libraries; Logic arrays; Logic functions; Programmable logic arrays;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206465
