Title :
An on-chip short-time interval measurement technique for testing high-speed communication links
Author :
Huang, Jiun-Lang ; Cheng, Kwang-Ting
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
In this paper, we present a BIST scheme for on-chip short-time interval measurement intended for characterizing the time-domain specifications, e.g., the rise/fall time of modern high-speed communication transceivers. To reduce hardware overhead, the proposed BIST technique uses the coherent under-sampling principle, and measures implicitly the time interval in a two-pass manner. Simulation results are shown to validate the proposed technique
Keywords :
built-in self test; integrated circuit measurement; logic testing; time measurement; time-domain analysis; transceivers; BIST scheme; coherent under-sampling principle; communication transceivers; hardware overhead; high-speed communication links; on-chip short-time interval measurement technique; rise/fall time; time interval; time-domain specifications; two-pass manner; Built-in self-test; Delay; Hardware; Jitter; Measurement techniques; Physical layer; Testing; Time domain analysis; Time measurement; Transceivers;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923466