Effect of Barrier layer thickness on device performance of AlInN/GaN Underlap DG MOSFET

We analyze the influence of Al_0.83In_0.17N barrier layer thickness (T_B) on device performance of 18nm gate length ultra thin body AlInN/GaN heterostructure underlap DG MOSFET, using 2D Sentaurus TCAD simulation. The device is designed according to the ITRS specifications and simulation is done using the hydrodynamic model. The simulation is validated with previously published experimental results. Very high drain current density (~8.8 mA/μm) is achieved, due to high values of two-dimensional electron gas (2DEG) density and velocity. Simulation of major device performance parameters such as DIBL, SS, delay, threshold voltage (V_t), ON current, energy delay product and total gate capacitance C_gg have been done for T_B ranging from 0nm to 4nm. As T_B is increased the drain current increases and delay decreases, but at the expense of loss of electrostatic control leading to increased short channel effect i.e. higher DIBL and SS. Also, negative shift in threshold voltage is observed for rising T_B. Decrease in C_gg is observed as T_B increases, due to increase in separation between the gate and channel, leading to reduced gate control. There is tradeoff between achieved drain current and electrostatic control for varying T_B Thus, the selection of appropriate T_B is of vital significance as it determines the device performance.