Title :
Performance enhancement in a fuzzy controlled digital phase locked loop
Author :
Chatterjee, Biswendu ; Ray, Sambaran ; Biswas, B.N.
Author_Institution :
Dept. of AEIE, Acad. of Technol., Hooghly, India
Abstract :
A Fuzzy logic controller is employed here for controlling a 1st order digital phase locked loop (DPLL) based on adaptive loop gain criterion. This intelligent loop is changing its loop gain to vary the loop bandwidth for providing rapid and accurate control of DPLL in the transient and steady states. This form of Fuzzy DPLL is further modified by the inclusion of an additional phase control in the digitally controlled oscillator (DCO). Moreover, the system level model of this proposed form of Fuzzy DPLL is implemented on a reconfigurable logic platform using System Generator®, a tool from Xilinx® used for FPGA design. Hardware simulations of all forms of DPLL confirm that proposed Phase controlled Fuzzy DPLL does achieve fast locking, reduction in tracking error, better noise immunity, large signal handling capacity and overall outperforming its other counterparts.
Keywords :
adaptive control; digital control; digital phase locked loops; field programmable gate arrays; fuzzy control; oscillators; phase control; reconfigurable architectures; transient analysis; DCO; DPLL steady state; DPLL transient state; FPGA design; Xilinx system generator; adaptive loop gain criterion; digitally controlled oscillator; fuzzy controlled digital phase locked loop; fuzzy logic controller; hardware simulation; large signal handling capacity; noise immunity; performance enhancement; phase control; tracking error reduction; Intelligent systems; Digital Phase Locked Loop (DPLL); Fuzzy DPLL; Modified DCO; Noise Bandwidth; Tone Modulation; Xilinx System Generator®;
Conference_Titel :
Communications, Devices and Intelligent Systems (CODIS), 2012 International Conference on
Conference_Location :
Kolkata
Print_ISBN :
978-1-4673-4699-3
DOI :
10.1109/CODIS.2012.6422248