A Combined Approach for Information Flow Analysis in Fault Tolerant Hardware

Fault tolerance in information security devices is difficult to establish due to the large number of possible interactions in the device (e. g. embedded code, boolean logic, electromagnetic interference, etc.) In previous work we examined information flow as a graph problem by composing orthogonal views of the device under analysis. In other work we used fault-tree analysis to reason about information flow as a systemic failure arising from certain configurations (or faults) in either the control logic or data flow ´backbone´. In this paper we combine these approaches by taking advantage of an alternative representation of fault trees as reliability block diagrams.