Chip Design of LPC-cepstrum for Speech Recognition

Author

Wu, Gin-Der ; Zhu, Zhen-Wei

Author_Institution

Nat. Chi Nan Univ., Puli

fYear

2007

fDate

11-13 July 2007

Firstpage

43

Lastpage

47

Abstract

This paper proposed an ASIC of LPC-cepstrum (LPCC) for speech recognition. The proposed ASIC of LPCC can reduce the calculation load of processor in the speech recognition system. In addition, the resource sharing method is adopted into our design in order to reduce the chip size. Hence, it does not give an emphasis on sophistication but on high- performance and low-cost solution. Finally, we did some experiments to compare with other DSP or ASIC design. We found that our proposed LPCC ASIC can efficiently reduce the computation load.

Keywords

application specific integrated circuits; integrated circuit design; logic design; resource allocation; speech recognition; application specific integrated circuits; linear predictive coefficient cepstrum chip design; resource sharing method; speech recognition system; Application specific integrated circuits; Autocorrelation; Chip scale packaging; Computer architecture; Costs; Digital signal processing chips; Hardware; Linear predictive coding; Resource management; Speech recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Information Science, 2007. ICIS 2007. 6th IEEE/ACIS International Conference on

Conference_Location

Melbourne, Qld.

Print_ISBN

0-7695-2841-4

Type

conf

DOI

10.1109/ICIS.2007.75

Filename

4276355