On the Limitations of Compilers to Exploit Thread-Level Parallelism in Embedded Applications

With the growing acceptance of multi-core architectures by the industry, devising novel techniques to extract thread-level parallelism from sequential programs has become a fundamental need. The role of compiler along with programming model and architectural innovation is of utmost importance to fully realize the potential performance benefits of the multi-core architectures. This paper evaluates the capabilities and limitations of parallelizing compilers to extract parallelism automatically from the loops present in sequential programs. The applications from embedded benchmark suites EEMBC 1.1 and MiBench are analyzed using the Intel C++ 9.1 Compiler for Linux. The contributions of the paper are manifold: Firstly, the paper shows that on average 10% of the loops can be parallelized automatically by the Intel Compiler. Secondly, we have shown that the auto- parallelizable loops cover only about 12.5% of the total program execution-time. Thirdly, we have explored the reasons behind the inability of the compiler to auto-parallelize the majority of the loops. We have found that on average 37.5% and 8% of the loops can´t be auto-parallelized because of statically unknown loop trip count and probable data dependence, respectively. Finally, this study identifies the set of loops which comprises the most of the execution time of the programs and shows that compiler, on average, can automatically parallelize about 22% of such loops.