Parallel packet forwarding architecture using ATM switch core for scalable performance

Author

Shiomoto, Kohei ; Omotani, Masaaki ; Uga, Masanori ; Shimizu, Shigeki

Author_Institution

NTT Network Service Syst. Labs., Tokyo, Japan

fYear

2001

fDate

2001

Firstpage

159

Lastpage

163

Abstract

This paper proposes a label switch router architecture using ATM switch core. Hardware-based forwarding engines are attached to the switch core in a scalable fashion in the proposed label switch router. Dimensioning the number of forwarding engines is proposed to achieve scalable performance. An ATM virtual circuit is used as label switched path in the MPLS network. Traffic management and OAM capabilities are applied to achieve carrier-grade network control for the network infrastructure the next generation Internet is to provide

Keywords

Internet; asynchronous transfer mode; computer network management; packet switching; parallel processing; quality of service; telecommunication control; telecommunication network routing; telecommunication traffic; transport protocols; ATM switch core; ATM virtual circuit; MPLS network; OAM; QoS; carrier-grade network control; forwarding engine dimensioning; hardware-based forwarding engines; label switch router architecture; label switched path; network infrastructure; next generation Internet; parallel packet forwarding architecture; scalable performance; traffic management; Asynchronous transfer mode; Packet switching; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Switching and Routing, 2001 IEEE Workshop on

Conference_Location

Dallas, TX

Print_ISBN

0-7803-6711-1

Type

conf

DOI

10.1109/HPSR.2001.923624

Filename

923624