Implementation of power optimized VLSI designs for reliable processing using majority circuit

Most of the applications require hard real time signal/data processing potentiality for which fast and dedicated VLSI architectures are the best solution. But designing such circuits lead to high occurrences of failure in the system. Hence there is a critical need for fault tolerance techniques for VLSI designs to increase the reliability of the system. Redundancy techniques are implemented widely to increase the reliability. By developing a fault tolerant system such as Triple Modular Redundancy (TMR), the FPGA can locate the errors and reconfigure the corrupted areas while maintaining the validity of system outputs. One of the drawbacks of this scheme is that the reliability of voter circuit is assumed to be perfect which may not be true. Hence, a novel fault-tolerant voter circuit (NFTVC) have been developed which is more reliable and leads to low power fault tolerant designs. Experimental results show that NFTVC is more reliable than the traditional TMR schemes. The hardware part of the design was done using Spartan-3 kit that is used for a rapid digital circuit. The system performance has been optimized using the Plan Ahead tool in Xilinx in order to reach and maintain the goals of the design. The implementation results provide a simultaneous improvement in power, delay and area.