Analog VLSI implementation of a neural network with competitive learning

Author

Pelayo, F.J. ; Prieto, A. ; Pino, Begona ; Martin-Smith, P.

Author_Institution

Dept. de Electron. y Tecnologie de Computadores, Granada Univ.

fYear

1990

fDate

16-19 Dec 1990

Firstpage

197

Lastpage

205

Abstract

An analog VLSI implementation of a neural network is presented which has been designed for use in clustered systems with competitive learning. The circuit implements an inhibitory cluster that includes the winner-unit computation. The synaptic weights are externally alterable asynchronously with network operation. A test chip has been designed with the rules of a 2-μm CMOS process which shows high integration density (about 200 synaptic connections per square millimeter). Simulation results and VLSI realization details of different modules comprised in the chip are also presented

Keywords

CMOS integrated circuits; VLSI; computerised pattern recognition; learning systems; linear integrated circuits; microprocessor chips; neural nets; parallel architectures; CMOS IC; analog VLSI; clustered systems; competitive learning; microprocessor chips; modules; neural network; winner-unit computation; Analog computers; Artificial neural networks; Brain modeling; Computational modeling; Computer networks; Concurrent computing; Neural network hardware; Neural networks; Neurons; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and their Applications, 1990. CNNA-90 Proceedings., 1990 IEEE International Workshop on

Conference_Location

Budapest

Type

conf

DOI

10.1109/CNNA.1990.207525

Filename

207525