Analog VLSI implementation of a neural network with competitive learning

An analog VLSI implementation of a neural network is presented which has been designed for use in clustered systems with competitive learning. The circuit implements an inhibitory cluster that includes the winner-unit computation. The synaptic weights are externally alterable asynchronously with network operation. A test chip has been designed with the rules of a 2-μm CMOS process which shows high integration density (about 200 synaptic connections per square millimeter). Simulation results and VLSI realization details of different modules comprised in the chip are also presented