III-V MOSFETs: Scaling laws, scaling limits, fabrication processes

Author

Rodwell, M.J.W. ; Singisetti, U. ; Wistey, M. ; Burek, G.J. ; Carter, A. ; Baraskar, A. ; Law, J. ; Thibeault, B.J. ; Kim, Eun Ji ; Shin, B. ; Lee, Yong-Ju ; Steiger, S. ; Lee, S. ; Ryu, H. ; Tan, Y. ; Hegde, G. ; Wang, L. ; Chagarov, E. ; Gossard, A.C. ;

Author_Institution

Depts. of ECE & Mater., Univ. of California, Santa Barbara, CA, USA

fYear

2010

fDate

May 31 2010-June 4 2010

Firstpage

1

Lastpage

6

Abstract

III-V FETs are in development for both THz and VLSI applications. In VLSI, high drive currents are sought at low gate drive voltages, while in THz circuits, high cutoff frequencies are required. In both cases, source and drain access resistivities must be decreased, and transconductance and drain current per unit gate width must be increased by reducing the gate dielectric thickness, reducing the inversion layer depth, and increasing the channel 2-DEG density of states. We here describe both nm self-aligned fabrication processes and channel designs to address these scaling limits.

Keywords

III-V semiconductors; MOSFET; VLSI; III-V MOSFET; THz circuits; VLSI applications; channel 2-DEG density; gate dielectric thickness; scaling laws; scaling limits; self-aligned fabrication processes; Circuits; Conductivity; Cutoff frequency; FETs; Fabrication; III-V semiconductor materials; Low voltage; MOSFETs; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Indium Phosphide & Related Materials (IPRM), 2010 International Conference on

Conference_Location

Kagawa

ISSN

1092-8669

Print_ISBN

978-1-4244-5919-3

Type

conf

DOI

10.1109/ICIPRM.2010.5515914

Filename

5515914