Low power components for 1 Gb/s optical communications: A single-chip 10-channel optical receiver and a clock recovery circuit

Author

Hickling, R.M. ; Kot, R.A. ; Yagi, M.N. ; Nagarajan, R. ; Sha, W.J. ; Craig, R.

Author_Institution

TechnoConcepts Inc., Newbury Park, CA, USA

fYear

1997

fDate

12-15 Oct. 1997

Firstpage

201

Lastpage

204

Abstract

A single chip, 10-channel optical transimpedance receiver and a low-power, single channel clock recovery circuit have been designed and characterized. The 10-channel receiver operates from a single 3.3 V or 5 V power supply, is capable of automatic offset correction, and generates ECL or PECL output levels. The clock recovery circuit operates from a single 5 V power supply and is based upon a novel variation on the so-called early-late gate bit synchronizer loop.

Keywords

LAN interconnection; clocks; emitter-coupled logic; optical interconnections; optical receivers; synchronisation; 1 Gbit/s; 3.3 V; 5 V; ECL output levels; LANs; PECL output levels; automatic offset correction; clock recovery circuit; early-late gate bit synchronizer loop; optical communications; optical interconnections; optical receiver; transimpedance receiver; Capacitors; Circuits; Clocks; Data buses; Delay; Feedback; High speed optical techniques; Optical devices; Optical receivers; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1997. Technical Digest 1997., 19th Annual

Conference_Location

Anaheim, CA, USA

ISSN

1064-7775

Print_ISBN

0-7803-4083-3

Type

conf

DOI

10.1109/GAAS.1997.628269

Filename

628269