Title :
Statistical delay fault coverage and defect level for delay faults
Author :
Park, E.S. ; Mercer, M.R. ; Williams, T.W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
A quantitative delay fault coverage model is discussed to provide a figure of merit for delay testing. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A statistical delay fault coverage model is established. A defect-level model is also proposed as a function of the yield of a manufacturing process and the statistical delay fault coverage
Keywords :
delays; logic testing; statistical analysis; defect level model; delay faults; delay testing; logic testing; propagation delay; quantitative delay fault coverage model; statistical model; Circuit faults; Circuit testing; Clocks; Delay effects; Fault detection; Logic testing; Propagation delay; Steady-state; System testing; Timing;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207761
