Title :
A network processor architecture for flexible QoS control in very high-speed line interfaces
Author :
Shimonishi, Hideyuki ; Murase, Tutomu
Author_Institution :
Comput. & Commun. Media Res., NEC Corp., Japan
Abstract :
We developed a network processor architecture that can be used for very high-speed line interfaces of carrier-class backbone routers and switches. Because advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism and enables effective header handling
Keywords :
multiprocessing systems; packet switching; parallel architectures; pipeline processing; processor scheduling; quality of service; telecommunication computing; telecommunication network routing; backbone switches; carrier-class backbone routers; effective header handling; flexible QoS control; network processor architecture; packet scheduling; packet switches; queuing; software routine; very high-speed line interfaces; Communication system control; Costs; Delay; Intelligent networks; Parallel processing; Pipeline processing; Quality of service; Scheduling algorithm; Spine; Switches;
Conference_Titel :
High Performance Switching and Routing, 2001 IEEE Workshop on
Conference_Location :
Dallas, TX
Print_ISBN :
0-7803-6711-1
DOI :
10.1109/HPSR.2001.923669
