IO standard based energy efficient ALU design and implementation on 28nm FPGA

In this work, target design is ALU. To achieve reduction in IOs power we are searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard. There is 85.18% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS12 based ALU design. There is 41.45% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS25 based ALU design. Target FPGA family is 28nm Artix-7. Verilog is hardware description language used for design of ALU. There is 7.16% reduction in power for only LVCMOS15, when we change drive strength from 16 milliAmpere to 8 milli-Ampere. There is 5.44% reduction in power for LVCMOS18 when we change drive strength from 24 milliAmpere to 8 milli-Ampere. LVCMOS33 is the highest power consumer and LVCMOS12 is the lowest power consumer among the different available LVCMOS IO standard when there is common drive strength applied.