Title :
Fault simulation and test pattern generation at the multiple-valued switch level
Author :
Caisso, J.-P. ; Courtois, B.
Author_Institution :
IMAG/TIM3, Grenoble, France
Abstract :
A fault simulation and test-pattern-generation environment is specified. It includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The authors´ main idea is to define what is possible when no extraction to gate level and no creation of transistor groups are performed. Two fault groups are distinguished: the faults which can be modelled in a downward layout, and the faults which can be modelled in an upward verification. This distinction induces difference in the switch network obtained, as the second group allows to model the line resistances
Keywords :
VLSI; digital simulation; fault location; integrated circuit testing; integrated logic circuits; logic testing; VLSI; bidirectional devices; downward layout; fault simulation; line resistances; logic testing; multiple-valued algebra; multiple-valued switch level; switch network; test pattern generation; upward verification; Algebra; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer architecture; Semiconductor device modeling; Switches; Switching circuits; Test pattern generators;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207785
