• DocumentCode
    3110437
  • Title

    A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

  • Author

    Hirose, Fumiyasu ; Takayama, Koichiro ; Kawato, Nobuaki

  • Author_Institution
    Fujitsu Lab. Ltd., Japan
  • fYear
    1988
  • fDate
    12-14 Sep 1988
  • Firstpage
    102
  • Lastpage
    107
  • Abstract
    A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP)
  • Keywords
    automatic testing; combinatorial circuits; digital simulation; integrated logic circuits; logic testing; combinational logic circuits; test generation; test patterns; ultrahigh-speed logic simulator; Automatic testing; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Combinational circuits; Computational modeling; Logic testing; Parallel processing; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1988. Proceedings. New Frontiers in Testing, International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-8186-0870-6
  • Type

    conf

  • DOI
    10.1109/TEST.1988.207786
  • Filename
    207786
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3110437