Parametric analyses on fatigue reliability of 3D IC packages with built through silicon vias (TSVs)

3D IC technology, an advanced IC package architecture, has drawn much interest in semi-conduct manufacturing. A 3-D integrated circuit is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. For this kind of package through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to many factors including design parameters such as via radius, via aspect ratio, via pitch, chip thickness, and underfill thickness. Presented in this paper are parametric analyses of the effects of selected design parameters on fatigue reliability of lead-free solder joints in a 3D IC package subjected to temperature cycling. The parameters considered are chip thickness, TSV pitch, TSV radius, underfill thickness, and the coefficient of thermal expansion of underfill. The results show that there is a monotonic down trend of the fatigue life as the chip thickness increases. Also, while the fatigue life decreases with via pitch, the radius of via is the least dominant parameter for present package.