DocumentCode :
3110555
Title :
Design for testability for wafer-scale integration interconnect systems design and test methodology
Author :
Gruetzner, Matthias
Author_Institution :
Inst. fuer Theor. Elektrotech., Hannover Univ., West Germany
fYear :
1988
fDate :
12-14 Sep 1988
Firstpage :
146
Lastpage :
152
Abstract :
A novel test approach for interconnects of laser configurable wafer-scale integration (WSI) systems is described. In this approach, buses are terminated by registers-called Echoregisters-which receive and reflect test signals. The test is carried out in the form of an echo and is therefore called Echotest. The test of the interconnect system is of crucial significance for WSI, because of the extensive interconnect systems that cover a large part of the chip area. Stuck-at, stuck-open, and stuck-on faults, including opens and shorts in the interconnect systems, which are assumed to include amplifiers, can be detected with the described Echotest. By this procedure it is sufficient to access the device under test by only one end. The hardware is half of that of a scan path, as used for the usual tests. The test hardware is realized in an experimental chip
Keywords :
VLSI; fault location; integrated circuit technology; integrated circuit testing; logic design; logic testing; modules; packaging; Echoregisters; Echotest; IC testing; echo; laser configurable wafer-scale integration; opens; registers; shorts; stuck open fault; stuck-at fault; stuck-on faults; wafer-scale integration interconnect systems; Built-in self-test; Design for testability; Fault detection; Hardware; Laser theory; Propagation delay; Redundancy; System testing; Very large scale integration; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-8186-0870-6
Type :
conf
DOI :
10.1109/TEST.1988.207792
Filename :
207792
Link To Document :
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