Self-aligned multilayer dielectric “dummy gate” technology for GaAs HFET fabrication

The main aspects of the technology for GaAs heterojunction metal-semiconductor field effect transistors fabrication have been demonstrated. The self-aligned technology with multilayer dielectric “dummy gate” used for fabrication of the transistor with 0.5 microns gate length, molecular beam epitaxy for channel and ion implantation for drain and source regions formation are described. The dependencies of the maximal drain-source current Idsmax, gate-drain breakdown voltage BVgd and extrinsic transconductance Gm as function of the gap between the gate and n+-drain region Lgd were investigated. The threshold voltage Vth uniformity and small-signal measurement of the fabricated transistor are demonstrated.