Hierarchical test generation using precomputed testsd for modules

A novel test-generation technique for large circuits with high fault-coverage requirements is described. Circuit modules and signals are represented at a high descriptive level. Test data for modules are represented by predefined stimulus/response packages which are processed symbolically using techniques derived from artificial intelligence. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. Preliminary results from a programmed implementation of the proposed test-generation technique are presented